User Input User Input User Input Probed Program Probed Executable Profile Information Probing Library

Instruction schedulers for superscalar and VLIW processors must expose suucient instruction-level parallelism to the hardware in order to achieve high performance. Traditional compiler instruction scheduling techniques typically take into account the constraints imposed by all execution scenarios in the program. However, there are additional opportunities to increase instruction-level parallelism for the frequent execution scenarios at the expense of the less frequent ones. Proole information identiies these important execution scenarios in a program. In this paper, two major categories of proole information are studied: control-ow and memory-dependence. Proole-assisted code scheduling techniques have been incorporated into the IMPACT-I compiler. These techniques are acyclic global scheduling and software pipelining. This paper describes the scheduling algorithms, highlights the modiications required to use proole information, and explains the hardware and compiler support for dealing with hazards that arise from aggressive use of proole information. The eeectiveness of these proole-based scheduling techniques is evaluated for a range of superscalar and VLIW processors.